Guest Editor's Introduction: Microprocessor Testing Today
IEEE Design & Test
Guest Editors' Introduction: Microprocessor Test and Verification
IEEE Design & Test
Test Development for a Third-Version ColdFire Microprocessor
IEEE Design & Test
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
At-Speed Built-in Test for Logic Circuits with Multiple Clocks
ATS '02 Proceedings of the 11th Asian Test Symposium
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor
ITC '04 Proceedings of the International Test Conference on International Test Conference
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
Journal of Computer Science and Technology
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This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.