At-Speed Built-in Test for Logic Circuits with Multiple Clocks

Authors:
Kazumi Hatayama;Michinobu Nakao;Yasuo Sato
Affiliations:
-;-;-
Venue:
ATS '02 Proceedings of the 11th Asian Test Symposium
Year:
2002

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Abstract

This paper presents an at-speed built-in test method forlogic circuits with multiple clocks. It is clear that BIST(built-in self-test) plays a key role in test strategy for SoCs.is also obvious that at-speed BIST is necessary for highquality test. Though several approaches enable at-speedBIST, there still exist several issues, such as multipleclocks, multi-cycle transfers and false paths. The proposedmethod realizes at-speed test for arbitrary combination ofrelease and capture clocks at reasonable test time byutilizing the LFSR reseeding technique. Experimentalresults for benchmark circuits and an industrial circuit aregiven to illustrate the effectiveness of our approach.