Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs
ATS '97 Proceedings of the 6th Asian Test Symposium
At-Speed Built-in Test for Logic Circuits with Multiple Clocks
ATS '02 Proceedings of the 11th Asian Test Symposium
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing of core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.