Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Test generation for designs with multiple clocks
Proceedings of the 40th annual Design Automation Conference
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Achieving At-Speed Structural Test
IEEE Design & Test
Control-Aware Test Architecture Design for Modular SOC Testing
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Wrapper Design for Testing IP Cores with Multiple Clock Domains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
IEICE - Transactions on Information and Systems
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This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. We present an integer linear programming (ILP) model that can be used to minimize the testing time for small problem instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances. Compared to recent work on wrapper design using a single shift frequency, we obtain lower testing times and the reduction in testing time is especially significant under power constraints.