Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
IEEE standard 1500 compatible delay test framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper deals with control-aware test architecture design for SOCs. The term test control refers to the control of mode of operation of all modules connected in different TAMs and the execution of the modules tests. We classify test control into two categories: (1) pseudo-static test control and (2) dynamic test control. Pseudo-static test control can be provided by means of a shift-register, where dynamic test control requires dedicated test pins. As the total number of chip pins available for test is limited, a large number of test control pins results in less TAMbandwidth available for test data. Therefore test architecture design should take the test control into account. To deal with pseudo-static test control for a given test architecture, we present two test strategies and discuss their impact on the corresponding test schedule. For dynamic test control, we present pin-constrained design of test architectures. Experimental results for the ITC'02 SOC Test Benchmarks show that the new pin-constrained design algorithm can save up to 42% in test time compared to the test times obtained from a conventional architecture design procedure.