Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Resistance Characterization for Weak Open Defects
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Control-Aware Test Architecture Design for Modular SOC Testing
ETW '03 Proceedings of the 8th IEEE European Test Workshop
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process-Variation and Temperature Aware SoC Test Scheduling Technique
Journal of Electronic Testing: Theory and Applications
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Recent research has shown that different defects can manifest themselves as failures at different temperature spectra. Therefore, we need multi-temperature testing which applies tests at different temperature levels. In this paper, we discuss the need and problems for testing core-based systems-on-chip at different temperatures. To address the long test time problem for multi-temperature test, we propose a test scheduling technique that generates the shortest test schedules while keeping the cores under test within a temperature interval. Experimental results show the efficiency of the proposed technique.