Signals & systems (2nd ed.)
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Low Power Design in Deep Submicron Electronics
Low Power Design in Deep Submicron Electronics
Test Power: a Big Issue in Large SOC Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design and implementation of the POWER5™ microprocessor
Proceedings of the 41st annual Design Automation Conference
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
The Scaling and Squaring Method for the Matrix Exponential Revisited
SIAM Journal on Matrix Analysis and Applications
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ATS '09 Proceedings of the 2009 Asian Test Symposium
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Temperature Dependent Test Scheduling for Multi-core System-on-Chip
ATS '11 Proceedings of the 2011 Asian Test Symposium
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.