Process-Variation and Temperature Aware SoC Test Scheduling Technique
Journal of Electronic Testing: Theory and Applications
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With scaling of technology and increasing design sizes, thermal issues are emerging to be one of the major concerns for modern Very-Large-Scale Integration (VLSI) testing due to both increasing power densities and higher reliability requirements. However, in all existing thermal-aware test scheduling research, test schedule is computed a priori as a static schedule using an estimate of the power consumed by each test. Due to the popular peak power model and increasing process variations, estimated test power values can be far from the actual power consumption. Consequently, the thermal profile of the chip estimated during off-line scheduling can be substantially different from that during actual testing. In this paper, we propose a dynamic thermal-aware test scheduling method using on-chip temperature sensors. We first define a test architecture that supports dynamic test scheduling and then develop a scheduling algorithm. Next, we perform simulation studies on ITC’02 benchmarks. Our simulation results show that the performance of the thermal aware test scheduling can be substantially improved with the help of on-chip temperature sensors, especially for chips with many cores.