Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

Authors:
Thomas Edison Yu;Tomokazu Yoneda;Krishnendu Chakrabarty;Hideo Fujiwara
Affiliations:
Nara Institute of Science and Technology, Kansai Science City, Japan;Nara Institute of Science and Technology, Kansai Science City, Japan;Duke University, Durham, NC;Nara Institute of Science and Technology, Kansai Science City, Japan
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

Citing 10
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Abstract

We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning, test interleaving, and bandwidth matching. We use a computationally tractable thermal-cost model to ensure that temperature constraints are satisfied and the test application time is minimized. Simulation results for the ITC'02 SOC Test Benchmarks show that, compared to prior thermal-aware test-scheduling techniques, the proposed method leads to shorter test times under tight temperature constraints.