Proceedings of the conference on Design, automation and test in Europe: Proceedings
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem by incorporating thermal constraints in the test scheduling of corebased systems. We propose two algorithms for which the objective is to spread heat more evenly over the chip and reduce hot spots. The first uses the layout information to guide test scheduling, while the second relies on a progressive weighting mechanism. Experimental results show that the proposed thermal-constrained methods can not only guarantee a thermal-safe test schedule, but also reduce hot spot temperatures, leading to a balanced thermal distribution across the chip during test.