Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
A matrix synthesis approach to thermal placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
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Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem in Network-on-Chip (NoC) systems through thermal optimization using variable-rate on-chip clocking. We control the core temperatures during test scheduling by assigning different test clock frequencies to cores. We present two heuristics to achieve thermal optimization and reduced test time. Experimental results for example NoC systems show that the proposed method can guarantee thermal safety and yield better thermal balance, compared to previous methods using power constraints. Test application time is also reduced.