Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture

Authors:
W. Hung;C. Addo-Quaye;T. Theocharides;Y. Xie;N. Vijaykrishnan;M. J. Irwin
Affiliations:
The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University
Venue:
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Year:
2004

Citing 0
Cited 16

Thermal-Aware Floorplanning Using Genetic Algorithms

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Key research problems in NoC design: a holistic perspective

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computation and communication refinement for multiprocessor SoC design: A system-level perspective

Proceedings of the 41st annual Design Automation Conference
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Journal of VLSI Signal Processing Systems
Integrated code and data placement in two-dimensional mesh based chip multiprocessors

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Achieving predictable performance through better memory controller placement in many-core CMPs

Proceedings of the 36th annual international symposium on Computer architecture
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip

Computers and Electrical Engineering
Recent thermal management techniques for microprocessors

ACM Computing Surveys (CSUR)
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Moths: Mobile threads for on-chip networks

ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping

Microprocessors & Microsystems
Efficient genetic based topological mapping using analytical models for on-chip networks

Journal of Computer and System Sciences
Design space exploration of thermal-aware many-core systems

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP cores or processing elements (PEs) interconnected by on-chip switching fabrics or routers. Hardware virtualization, which maps logic processing units onto PEs, affects the power consumption of each PE and the communications among PEs. The communication among PEs affects the overall performance and router power consumption, and it depends on the placement of PEs. Therefore, the temperature distribution profile of the chip depends on the IP core virtualization and placement. In this paper, we present an IP virtualization and placement algorithm for generic regular Network on Chip (NoC) architecture. The algorithm attempts to achieve a thermal balanced design while minimizing the communication cost via placement. Our framework can also realize hardware virtualization which can further accomplish better performance. A case study on Low Density Parity Checks (LDPC) decoder is presented to evaluate our algorithm.