A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Thermal Impacts on NoC Interconnects
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proactive temperature balancing for low cost thermal management in MPSoCs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
High performance computing architectures
Computers and Electrical Engineering
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
Computers and Electrical Engineering
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Deadlock-Free Adaptive Routing in Meshes with Fault-Tolerance Ability Based on Channel Overlapping
IEEE Transactions on Dependable and Secure Computing
Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
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Network-on-Chip (NoC) replaces the traditional bus-based architecture to become the mainstream design methodology for future complex System-on-Chip (SoC). It introduces the principles of packet switching and interconnection network into SoC design, and achieves much better performance for its high bandwidth, scalability, reliability, etc. However, thermal problem, such as regional temperature differential and hotspot, is still one of the main designing constraints. This paper proposes a dynamic thermal-balance routing (DTBR) algorithm for Network-on-Chip, which can solve both of the two thermal problems. DTBR is a minimal adaptive routing algorithm based on an architectural thermal model. An efficient thermal-aware router is designed to implement the DTBR algorithm. According to the simulation results, the proposed DTBR algorithm can make the network thermal distribution more uniform and hotspot temperature is cut down about 20% in different traffic patterns. Moreover, DTBR will bring a profit for the performance of packet delay and network throughput compared with other routing algorithms.