Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking

Authors:
Chunsheng Liu;Vikram Iyengar;D. K. Pradhan
Affiliations:
University of Nebraska-Lincoln;IBM Microelectronics;University of Bristol, UK
Venue:
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Year:
2006

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Abstract

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...