Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
MIX: A Test Generation System for Synchronous Sequential Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Reducing Average and Peak Test Power Through Scan Chain Modification
Journal of Electronic Testing: Theory and Applications
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Proceedings of the conference on Design, automation and test in Europe
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low-Transition Test Pattern Generation for BIST-Based Applications
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fault modeling for FinFET circuits
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Low-power FinFET circuit synthesis using surface orientation optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Gated-diode FinFET DRAMs: Device and circuit design-considerations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dual- Independent-Gate FinFETs for Low Power Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power consumption has become a very important consideration during integrated circuit (IC) design and test. During test, it can far exceed the values reached during normal operation and, thus, lead to temperatures above the allowed threshold. Without appropriate temperature reduction, permanent damage may be caused to the IC or invalid test results may be obtained. FinFET is a double-gate field-effect transistor (DG-FET) that was introduced commercially in 2012. Due to the vertical nature of FinFETs and, hence, weaker ability to dissipate heat, this problem is likely to get worse for FinFET circuits. Another technology rapidly gaining popularity is 3D IC integration. Unfortunately, the compact nature of a multidie 3D IC is likely to aggravate the temperature-during-test problem even further. Hence, before temperature-aware test methodologies can be developed, it is important to thermally analyze both FinFET and 3D circuits under test. In this article, we present a methodology for thermal characterization of various test techniques, such as scan and built-in self-test (BIST), for FinFET and 3D ICs. FinFET thermal characterization makes use of a FinFET standard cell library that is characterized with the help of the University of Florida double-gate (UFDG) SPICE model. Thermal profiles for circuits under test are produced by ISAC2 from University of Colorado for FinFET circuits and HotSpot from University of Virginia for 3D ICs. Experimental results indicate that high temperatures result under BIST and much less often under scan, and that both power consumption and test application time should be reduced to lower the temperature of circuits under test, just reducing the power consumption is not enough.