Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Power-Time Tradeoff in Test Scheduling for SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Thermal-aware scheduling for future chip multiprocessors
EURASIP Journal on Embedded Systems
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.