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For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to Built-In Self Test (BIST) can represent a significant percent age of the overall power dissipation. One possible solution to address this problem consists of test pattern sequence reordering with the purpose of reducing the amount of power dissipated during circuit testing. By reordering test pattern sequences one is able to minimize power dissipation. Moreover, a key observation is that test patterns are in general expected to exhibit don't cares, which can naturally be exploited during test pattern sequence reordering. In this paper we develop an optimization model and describe an efficient algorithm for reordering pattern sequences in the presence of don't cares. Preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering using don't cares can be significant.