Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Artificial Intelligence: A Modern Approach
Artificial Intelligence: A Modern Approach
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Evaluation of heuristic techniques for test vector ordering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
| Hi-index | 0.00 |
Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reordering for dynamic power minimization during combinational circuit testing is a sub-problem of the general goal of low power testing. The reordering is the process in which the sequence of applying test vectors is altered to reduce power dissipation. Power dissipation in CMOS circuits has two components: static, due to leakage current; and dynamic, due to switching activity. In this project, Artificial Intelligent (AI) based approach is presented to reorder the test vectors such that the minimum switching activity and hence the power dissipation during testing. In this method the hamming distance between successive test vectors is used to reorder the sequence. AI based reordering algorithm is implemented in Matlab and experimented with ISCAS85 benchmark circuits. Results show that the reordered test set minimized the testing power considerably when compared with unordered test set. Experimental results show that the proposed method reduces 30.15% of average power and 34.56% of the peak power when the reordered test vectors are used for testing.