Genetic Algorithm based Approach for Low Power Combinational Circuit Testing

Authors:
Santanu Chattopadhyay;Naveen Choudhary
Affiliations:
-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

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Abstract

With the advancement in automation, periodic testingof electronic circuits during their lifetime is becomingmore and more important. For such a circuit,it is thus very much necessary to reduce the powerrequirement during the testing phase also. This paperpresents a Genetic Algorithm based formulation tosolve the problem of generating a test pattern set suchthat it has high fault coverage and low power consumption.Exhaustive experimentation done on ISCAS85combinational benchmark suite has shown that the thistool results in upto 78% reduction in transition activityover the original test set generated by ATPGs likeATALANTA [1].