HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
ATPG for Heat Dissipation Minimization During Test Application
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Power Optimization Techniques for CMOS Circuits
ATS '02 Proceedings of the 11th Asian Test Symposium
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Leakage and leakage sensitivity computation for combinational circuits
Proceedings of the 2003 international symposium on Low power electronics and design
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Runtime leakage power estimation technique for combinational circuits
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on the activity in the circuit and hence depends on the sequence in which the test vectors are fed to it. We present an approach based on Particle Swarm Optimization (PSO) for vector reordering. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. We achieve a maximum of 86.63% at an average of 60.89% reduction in dynamic power, a maximum of 6.87% at an average of 5.28% savings in terms of leakage power and a maximum of 66.55% at an average of 50.11% savings in terms of total power with respect to the original compacted test set generated by Tetramax ATPG tool.