Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Novel ATPG Method for Capture Power Reduction during Scan Testing
IEICE - Transactions on Information and Systems
On Detection of Bridge Defects with Stuck-at Tests
IEICE - Transactions on Information and Systems
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2009 International Conference on Computer-Aided Design
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the Conference on Design, Automation and Test in Europe
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Test data compression based on geometric shapes
Computers and Electrical Engineering
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Integration, the VLSI Journal
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
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Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit, some of the primary input values may be changed to the opposite logic values without losing fault coverage. We can regard such input values as don't care (X). In this paper, we propose a method for identifying the X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including as many X inputs as possible, by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms. Experimental results for ISCAS benchmark circuits show that approximately 69% of the inputs of uncompacted test sets could be X on the average. Even for highly compacted test sets, the method found that approximately 48% of inputs are X.