Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing

Authors:
S. Krishna Kumar;Subhadip Kundu;Santanu Chattopadhyay
Affiliations:
Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India;Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India;Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India
Venue:
Integration, the VLSI Journal
Year:
2012

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Abstract

In this work, we propose a technique to reduce switching activity while keeping leakage current under control during testing by extracting don't cares from a completely specified pattern set, and using the X bits to convert original vectors into low power vectors by a dictionary based approach. We also investigate the possibility of reducing test set length, maintaining fault coverage, by performing a tradeoff between test set volume and power. Experiments on ISCAS89 benchmark circuits validate effectiveness of our work. We could achieve an average reduction of 84.78% in dynamic power and 6.52% in leakage power for pattern set generated by the ATPG tool Atalanta. Similar savings could also be achieved on test set generated by the commercial ATPG tool Tetramax.