ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compact test sets for high defect coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression technique using selective don't-care identification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On test data compression using selective don't-care identification
Journal of Computer Science and Technology
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
A new low energy BIST using a statistical code
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A scalable method for the generation of small test sets
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don't care (X). In this paper, we propose a method for identifying X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including X inputs as many as possible, by using fault simulation and procedures similar to implication and justification of ATPG algorithms. Experimental results for ISCAS benchmark circuits show that approximately 66% of inputs of un-compacted test sets could be X in average. Even for compacted test sets, the method found that approximately 47% of inputs are X. Finally, we discuss how logic values are reassigned to the identified X inputs where several applications exist to make test vectors more desirable.