IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Test Transformation to Improve Compaction by Statistical Encoding
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Don't-Care Identification on Specific Bits of Test Patterns
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Proceedings of the conference on Design, automation and test in Europe
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a test compression method that effectively derives the capability of a run-length based encoding. The method employs two techniques: scan polarity adjustment and pinpoint test relaxation. Given a test set for a full-scan circuit, scan polarity adjustment selectively flips the values of some scan cells in test patterns. It can be realized by changing connections between two scan cells so that the inverted output of a scan cell, Q, is connected to the next scan cell. Pinpoint test relaxation flips some specified 1s in the test patterns to 0s without any fault coverage loss. Both techniques are applied by referring to a gain-penalty table to determine scan cells or bits to be flipped. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could reduce test data volume by 36%. Switching activities, i.e. test power during scan testing, were also reduced.