IEEE Transactions on Computers
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computers and Electrical Engineering
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
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In test compression / decompression schemes the objective is to achieve the highest compression without sacrificing fault coverage. In this paper, we propose a method to transform a test set in order to achieve higher compression without sacrificing fault coverage, while using statistical encoding techniques. The compression ratio of a test set depends on the entropy of the test set, and hence our test transformation method decreases the entropy of the test set without losing the fault coverage. Experimental results show that the proposed method transforms given test sets into highly compressible ones.