ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
The Third Millennium's Test Dilemma
IEEE Design & Test
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
Test Transformation to Improve Compaction by Statistical Encoding
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
DFT for High-Quality Low Cost Manufacturing Test
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integratorýs standpoint considering a core based SOC environment. The proposed analysis addresses four parameters: compression ratio, test application time, area overhead and power dissipation. Based on our analysis, some future research directions are given which can lead to an easier integration of TDC in the SOC design flow and to further improve the four parameters.