Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of test data compression techniques emphasizing statistical coding schemes
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
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The semiconductor industry is capable of building "Tester-limited fabs" and definitely needs a more cost-effective solution for the cost of test problem than the one we have today. The solutions are likely to come from several different sources. While the ATE industry is addressing the cost of test problem by designing new DFT testers, it is the EDA industry that holds the key to providing an embedded test solution that guarantees high-quality low cost manufacturing test. In this presentation we examine various DFT technologies and their ability to provide high quality low cost manufacturing test.