Scan Vector Compression/Decompression Using Statistical Coding

Authors:
Abhijit Jas;Jayabrata Ghosh-Dastidar;Nur A. Touba
Affiliations:
-;-;-
Venue:
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Year:
1999

Citing 7
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Abstract

A compression/decompression scheme based on statistical coding is presented for reducing the amount of test data that must be stored on a tester and transferred to each core in a core-based design. The test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core. Given the set of test vectors for a core, a statistical code is carefully selected so that it satisfies certain properties. These properties guarantee that it can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) which requires very small area. Results indicate that the proposed scheme can use a simple decoder to provide test data compression near that of an optimal Huffman code. The compression results in a two-fold advantage since both test storage and test time are reduced.