Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Many chip designs contain one or more serial multipliers. A scheme is proposed to exploit this to compress the amount of data that needs to be stored on the tester and transferred to the CUT during manufacturing test. The test vectors are stored on the tester in a compressed format by expressing each test vector as a product of two numbers. While performing multiplication on these stored seeds in the Galois Field modulo 2, GF(2), the multiplier states (i.e. the partial products) are tapped to reproduce the test vectors and fill the scan chains. In contrast with other test vector decompression schemes that add significant test specific hardware to the chip, the proposed scheme reduces hardware overhead by making use of existing functional circuitry. Experimental results demonstrate that a high encoding efficiency can be achieved using the proposed scheme.