IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
Two-Dimensional Test Data Decompressor for Multiple Scan Designs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
High Speed Ring Generators and Compactors of Test Data
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Decompression of test data using variable-length seed LFSRs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Vector Compression Using EDA-ATE Synergies
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
XMAX: X-Tolerant Architecture for MAXimal Test Compression
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Electrical Engineering
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a 3-stage continuous-flow lineardecompression scheme for scan vectors that uses avariable number of bits to encode each vector. By using3-stages of decompression, it can efficiently compressany test cube (i.e., deterministic test vector where theunassigned bit positions are left as don't cares)regardless of the number of specified (care) bits. As aresult of this feature, there is no need for any constraintson the automatic test generation process (ATPG)process. Any ATPG can be used with any amount ofstatic or dynamic compaction. Experimental results areshown which demonstrate that the proposed schemeachieves extremely high encoding efficiency.