Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers - Special issue on fault-tolerant computing
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
The Third Millennium's Test Dilemma
IEEE Design & Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
ATPG versus Logic BIST -Now and in the Future
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A common approach for large industrial designs is touse logic built-in self-test (LBIST) followed by test datafrom an external tester. Because the fault coverage withLBIST alone is not sufficient, there is a need to top-up thefault coverage with additional deterministic test patternsfrom an external tester. This paper proposes a techniqueof combining LBIST and deterministic ATPG to form"hybrid test patterns" which merge pseudo-random anddeterministic test data. Experiments have been done onthe Motorola PowerPCTM microprocessor core to studythe proposed hybrid test patterns. Hybrid test patternsprovide several advantages: 1) can be applied usingSTUMPS architecture [Bardell 82] with a minormodification, 2) significantly reduce external test datastored in tester memory, 3) reduce the number of pseudorandompatterns by orders of magnitude, thus addressingpower issues.