Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Impact of Test Point Insertion on Silicon Area and Timing during Layout
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Survey of Test Vector Compression Techniques
IEEE Design & Test
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Hybrid BIST Optimization Using Reseeding and Test Set Compaction
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Historical Perspective on Scan Compression
IEEE Design & Test
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self-Test mechanism (BIST) a promising feature to be integrated in current IC flows. There are a lot of types of BIST: Memories BIST, Logical BIST (LBIST) and also some mechanisms used to test analog parts of circuit. Traditional LBIST uses on-chip hardware to generate all test patterns with a pseudo-random-pattern-generator (PRPG) and analyzes the output signature generated by a multiple-input-signature-register (MISR). This approach requires the insertion of extra test-points or storing information outside chip to enable achieving a test coverage 98%. Also generating all test stimuli implies in a sacrifice of test application time, which can be acceptable for some small systems to perform self-test during boot up but could become a negative aspect when testing System-on-chip (SOC) ICs. The current IC development flow insert scan chains and generates automatically scan tests patterns to achieve high fault coverage for manufacturing test. Scan data compression techniques have proven to be very useful for reducing test cost while reducing test data volume and test application time. This work proposes the reuse of compressed scan test patterns used during manufacturing test to implement a LBIST with the goal of testing the circuit when it is already in field. The proposed LBIST mechanism aims to uncover defects that could occur due to the wear out of the circuit. A scan test pattern based LBIST architecture and a semi-automatic development flow are proposed and validated in a real word SoC testcase.