Impact of Test Point Insertion on Silicon Area and Timing during Layout
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
MERO: A Statistical Approach for Hardware Trojan Detection
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Journal of Electronic Testing: Theory and Applications
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Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means of Test Point Insertion (TPI). The state-of-the-art TPI methods only focus on solving one or two possible testability problems,and sometimes even fail to result in test set size reduction because they focus on the wrong testability problem. In this paper we propose two TPI pre-process methods that analyze the circuit and select the TPI method that will focus on the testability problems that really exist. Experimental results indicate that with these pre-processes better test set size reductions can be achieved.Gate-delay fault ATPG test sets tend to be even larger than stuck-at fault ATPG test sets. In this paper we have evaluated the impact of TPI on gate-delay fault test sets. Experimental results indicate that TPI also results in a significant test set size reduction for gate-delay fault ATPG.