Impact of Test Point Insertion on Silicon Area and Timing during Layout

Authors:
Harald Vranken;Ferry Syafei Sapei;Hans-Joachim Wunderlich
Affiliations:
-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Year:
2004

Citing 8
Cited 3

A hybrid algorithm for test point selection for scan-based BIST

DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST

Proceedings of the IEEE International Test Conference on Test and Design Validity
An effort-minimized logic BIST implementation method

Proceedings of the IEEE International Test Conference 2001
Test Point Insertion for Compact Test Sets

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Test Mode Selection & Insertion for RTL-BIST

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume

ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A linear programming approach for minimum NBTI vector selection

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an experimental investigation on the impact of test point insertion on circuit size and performance. Often test points are inserted into a circuit in order to improve the circuit's testability, which results in smaller test data volume, shorter test time, and higher fault coverage. Inserting test points however requires additional silicon area and influences the timing of a circuit. The paper shows how placement and routing is affected by test point insertion during layout generation. Experimental data for industrial circuits show that inserting 1% test points in general increases the silicon area after layout by less than 0.5% while the performance of the circuit may be reduced by 5% or more.