A hybrid algorithm for test point selection for scan-based BIST

Authors:
Huan-Chih Tsai;Chih-Jen Lin;Sudipta Bhawmik;Kwang-Ting Cheng
Affiliations:
Department of ECE, University of California, Santa Barbara, CA;Intel Corporation, 5200 N.E. Elam Young Pkwy., Hillsboro, OR;Bell Laboratories, Lucent Technologies, Princeton, NJ;Department of ECE, University of California, Santa Barbara, CA
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

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Abstract

We propose a new algorithm for test point selection forscan-based BIST.The new algorithm combines the advantagesof both explicit-testability-calculation and gradienttechniques.The test point selection is guided by acost function which is partially based on explicit testabilityrecalculation and partially on gradients.With anevent-driven mechanism, it can quickly identify a set ofnodes whose testability need to be recalculated due toa test point, and then use gradients to estimate the impactof the rest of the circuit.In addition, by incorporatingtiming information into the cost function, timingpenalty caused by test points can be easily avoided.Wepresent the results to illustrate that high fault coveragesfor both area- and timing-driven test point insertionscan be obtained with a small number of test points.Theresults also indicate a significant reduction of computationalcomplexity while the qualities are similar to theexplicitly-testability-calculation method.