The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths in VLSI digital circuits
Behavioral synthesis of highly testable data paths in VLSI digital circuits
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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This paper presents an efficient estimation method for incremental testability analysis, which is based partially on explicit testability re-calculation and partially on gradient techniques. The analysis results have been used successfully to guide design transformations and partial scan selection. Experimental results on a variety of benchmarks show that the quality of our incremental testability analysis is similar to those of the conventional explicit testability re-calculation methods and the technique can be used efficiently for improving thetestability of a design during the high-level test synthesis andpartial scan selection processes.