Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Scheduling and allocation problems in high-level synthesis
Scheduling and allocation problems in high-level synthesis
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
High-level test synthesis for delay fault testability
Proceedings of the conference on Design, automation and test in Europe
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Contrary to other works in which scheduling and allocation are performed independently, our approach integrates these two tasks by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. The approach is based on an algorithm which applies a sequence of semantics-preserving transformations to a design to generate an efficient RT level implementation from a VHDL behavioral specification. Experimental results show the advantages of the proposed algorithm.