The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Compiling pascal programs into silicon (design automation, hardware synthesis)
Compiling pascal programs into silicon (design automation, hardware synthesis)
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Software methodologies for VHDL code static analysis based on flow graphs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
A Controller Testability Analysis and Enhancement Technique
EDTC '97 Proceedings of the 1997 European conference on Design and Test
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
Integration, the VLSI Journal
Design for testability reuse in synthesis for testability
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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