Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Logic synthesis
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Logic optimization by an improved sequential redundancy addition and removal techniques
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Symbolic optimization of FSM networks based on sequential ATPG techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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