How to efficiently build VHDL testbenches
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Functional verification of the CMOS S/390 parallel enterprise server G4 system
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Commercial Design Verification: Methodology and Tools
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design-For-Debug in Hardware/Software Co-Design
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An overview on writing a VHDL testbench
SSST '97 Proceedings of the 29th Southeastern Symposium on System Theory (SSST '97)
Formal verification-a viable alternative to simulation?
IVC '96 Proceedings of the 1996 IEEE International Verilog HDL Conference (IVC '96)
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
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Scalability and customization properties of IPmodules demand for new approaches in functional verification.We present a novel simulation-based solution for anApplication-Specific Instruction-set Processor (ASIP). Existingassembler code preselected by IP-configurable constraintsforms the verification data base (reference stimuli).A behavioral "golden model" of the IP is used to deriveexpected responses suitable for any possible configurationof the final ASIP (RTL) implementation. Cycle-based verificationis performed by stimulating the RTL model with theassembled reference stimuli and by comparing the outputs(actual responses) against the expected responses. Primaryinput stimulation is accomplished by reading back interfacedata prior written to a memory (model) under controlof the reference stimuli. The synchronization of theconfiguration-dependent actual responses to the non-cycle-relatedexpected responses is achieved by a mechanismbased on "interface-specific activity scheduling", whichfurther more reduces the number of vectors efficiently, resultingin a significant simulation speed-up.