A methodology to reduce the computational cost of behavioral test pattern generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Speed up of behavioral A.T.P.G. using a heuristic criterion
DAC '93 Proceedings of the 30th international Design Automation Conference
Speeding up test pattern generation from behavioral VHDL descriptions containing several processes
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
BDD-based testability estimation of VHDL designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A fault model for VHDL descriptions at the register transfer level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
From Design Validation to Hardware Testing: A Unified Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Virtual fault simulation of distributed IP-based designs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
A Behavioral Fault Simulator for Ideal
IEEE Design & Test
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
SystemC
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A framework for the functional verification of systemC models
International Journal of Parallel Programming
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancement of fault injection techniques based on the modification of VHDL code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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