Speeding up test pattern generation from behavioral VHDL descriptions containing several processes

Authors:
L. Vandeventer;J. F. Santucci
Affiliations:
Laboratoire d'Etude et de Recherche en Informatique, EERIE, Part Scientifique G. BESSE, 30000 Nîmes-France;Laboratoire d'Etude et de Recherche en Informatique, EERIE, Part Scientifique G. BESSE, 30000 Nîmes-France
Venue:
EURO-DAC '94 Proceedings of the conference on European design automation
Year:
1994

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