Micro-operation perturbations in chip level fault modeling
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Functional testing techniques for digital LSI/VLSI systems
DAC '84 Proceedings of the 21st Design Automation Conference
A methodology to reduce the computational cost of behavioral test pattern generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Speed up of behavioral A.T.P.G. using a heuristic criterion
DAC '93 Proceedings of the 30th international Design Automation Conference
Speeding up test pattern generation from behavioral VHDL descriptions containing several processes
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
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A new approach to test generation from Hardware Description Language circuit models has been developed and implemented. The described E-algorithm generates tests for control, operation, and data faults in sequential and combinational logic modeled at the functional level. A symbolic variable notation is introduced to permit systematic fault propagation through control structures. Results of the implementation are given for a set of test cases and the application of the algorithm to a semi-custom ASIC are discussed.