Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique

On behavior fault modeling for digital designs

Journal of Electronic Testing: Theory and Applications

Fault simulation using small fault samples

Journal of Electronic Testing: Theory and Applications

Estimation of average switching activity in combinational and sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Bridge fault simulation strategies for CMOS integrated circuits

DAC '93 Proceedings of the 30th international Design Automation Conference

Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy

DAC '93 Proceedings of the 30th international Design Automation Conference

A fault model for VHDL descriptions at the register transfer level

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Fault Sampling Revisited

IEEE Design & Test

A new architectural-level fault simulation using propagation prediction of grouped fault-effects

ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors

Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation

Proceedings of the IEEE International Test Conference on Test and Design Validity

Improving Gate Level Fault Coverage by RTL Fault Grading

Proceedings of the IEEE International Test Conference on Test and Design Validity

Bridging Defects Resistance Measurements in a CMOS Process

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design

Physical DFT for High Coverage of Realistic Faults

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design

Process-tolerant test with energy consumption ratio

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them

Testing embedded-core based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Defect-oriented test quality assessment using fault sampling and simulation

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them

13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

On the decline of testing efficiency as fault coverage approaches 100%

VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium

Test preparation for high coverage of physical defects in CMOS digital ICs

VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium

Inductive Fault Analysis of MOS Integrated Circuits

IEEE Design & Test

Testing CMOS logic gates for realistic shorts

ITC'94 Proceedings of the 1994 international conference on Test

Charge-based fault simulation for CMOS network breaks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems