A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Transient power supply current monitoring—a new test method for CMOS VLSI circuits
Journal of Electronic Testing: Theory and Applications
Digital Integrated Circuit Testing using Transient Signal Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Monitoring power dissipation for fault detection
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An approach to dynamic power consumption current testing of CMOS ICs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Detection and location of faults and defects using digital signal processing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Exploring the combination of IDDQ and iDDt testing: energy testing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Deep submicron defect detection with the energy consumption ratio
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Performance Comparison of VLV, ULV, and ECR Tests
Journal of Electronic Testing: Theory and Applications
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Analysis of the Delay Defect Detection Capability of the ECR Test Method
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Detecting Delay Faults using Power Supply Transient Signal Analysis
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Practical Application of Energy Consumption Ratio Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Statistical Threshold Formulation For Dynamic Idd Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect Detection using Power Supply Transient Signal Analysis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scaling of iDDT Test Methods for Random Logic Circuits
Journal of Electronic Testing: Theory and Applications
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We develop a new technique for fault detection based on a new metric, the energy consumptionratio(ECR). ECR-based test can detect faults, such asredundant faults, that escape detection with other techniques. Though the ECR is a metric based on the supplycurrent, an analog parameter, it is remarkably tolerant to the impact of process variations. The quality ofECR-based test is demonstrated through extensive simulation on a process offered by MOSIS. We also presenta test generation algorithm for the new test technique.When applied to benchmark circuits, this technique reliably detects a large fraction of the combinationally redundant faults in them.