Current Testing Procedure for Deep Submicron Devices
Journal of Electronic Testing: Theory and Applications
LEAP: An Accurate Defect-Free IDDQ Estimator
Journal of Electronic Testing: Theory and Applications
Process-tolerant test with energy consumption ratio
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Current Testing Procedure for Deep Submicron Devices
ETW '00 Proceedings of the IEEE European Test Workshop
LEAP: An Accurate Defect-Free IDDQ Estimator
ETW '00 Proceedings of the IEEE European Test Workshop
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Current Signatures: Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
IDDQ Characterization in Submicron CMOS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
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The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence of a large of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ sensing circuitry. In this work, we present a method to estimate the non-defective I/sub DDQ/ consumption based on a hierarchical approach using layout (device), electrical (cell) and logic (circuit) information. The maximum of the defect-free I/sub DDQ/ is obtained with a technique based on ATPG. The results show that the proposed method gives the maximum defect-free I/sub DDQ/ for small circuits. For large circuits, heuristics to find lower and upper bounds of the maximum defect-free I/sub DDQ/ are presented. Uncertainty margins lower than 15% have been found in the circuits experimented on.