Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Binning for IC Quality: Experimental Studies on the SEMATECH Data
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
IC Performance Prediction System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On the Effect of ISSQ Testing in Reducing Early Failure Rate
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Production-Oriented Measurement Method for Fast and Exhaustive Iddq Tests
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Successful Implementation of Structured Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Delta-IDDQ-based test methods
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Evaluation of Early Failure Screening Methods
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Reliabilty, Test, and IDDQ Measurements
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Model-Based IDDQ Pass/Fail Limit Setting
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
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This paper proposes a new ethodology for esti ating theupper bound on the IDDQ of defect free chips by using waferlevel spatial infor ation.This can be used for IDDQSEMATECH data.Such a methodology accounts for thechange in IDDQ due to process variations across wafers andreduces false rejects resulting in yield loss.Typicalscenarios in using this approach are discussed.The resultsare compared with traditional methods.