Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study

Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Estimating Burn-In Fall-Out for Redundant Memory

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Improved Wafer-level Spatial Analysis for IDDQ Limit Setting

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures: An Experimental Study

ITC '99 Proceedings of the 1999 IEEE International Test Conference

IDDQ data analysis using neighbor current ratios

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip

Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers

IEEE Design & Test

Test scheduling for wafer-level test-during-burn-in of core-based SoCs

Proceedings of the conference on Design, automation and test in Europe

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Power management using test-pattern ordering for wafer-level test during burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Adapting to adaptive testing

Proceedings of the Conference on Design, Automation and Test in Europe

Estimation of fault-free leakage current using wafer-level spatial information

IEEE Transactions on Very Large Scale Integration (VLSI) Systems