Test scheduling for wafer-level test-during-burn-in of core-based SoCs

Authors:
Sudarshan Bahukudumbi;Krishnendu Chakrabarty;Richard Kacprowicz
Affiliations:
Duke University, Durham, NC;Duke University, Durham, NC;Intel Corporation, Hillsboro, OR
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

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Abstract

Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. We present a test-scheduling technique for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Simulation results are presented for two ITC'02 SoC benchmarks, and the proposed technique is compared with two baseline methods.