Estimating Burn-In Fall-Out for Redundant Memory

  • Authors:
  • Thomas S. Barnett;Adit D. Singh;Victor P. Nelson

  • Affiliations:
  • -;-;-

  • Venue:
  • ITC '01 Proceedings of the 2001 IEEE International Test Conference
  • Year:
  • 2001

Quantified Score

Hi-index 0.00

Visualization

Abstract

Integrated circuits can exhibit significant early life orinfant mortality failures.Methods to estimate and/orreduce the number of such failures are therefore of greatinterest to industry.Applications employing multi-chipmodules (MCMs), where several die must be independentlyreliable, are particularly vulnerable to early lifefailures.Maximizing the reliability of each die is thereforeof significant importance.This paper presents anintegrated yield-reliability model that allows one to estimatethe number of burn-in failures for repairablememory chips, a common component in many MCMsBecause defects in integrated circuits tend to cluster,memory chips that have been repaired have a greaterchance of containing a latent defect than chips withno repairs.The result is a higher incidence of infantmortality failure among memory chips that have beenrepaired.